1. Field of the Invention
The present invention relates to an active bias circuit and more particularly, to an active bias circuit with a combined configuration of the Wilson configuration for current source and the Widlar configuration for current source.
2. Description of the Related Art
FIG. 1 shows a conventional active bias circuit 10 having a combined configuration of the Wilson and Widlar current source configurations As shown in FIG. 1, this bias circuit 10 comprises four n-channel Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) M11, M12, M13, and M14 and a resistor R11.
Each of the MOSFETs M11 and M14 has a so-called diode connection. Thus, the gate and the drain of the MOSFET M11 are coupled together at the point P1 and the gate and the drain of the MOSFET 14 are coupled together at the point P2. The drain of the MOSFET M11 is connected to the terminal T1 by way of the resistor R11 while the gate of the MOSFET M11 is connected to the gate of the MOSFET M13. The source of the MOSFET M11 is connected to the drain of the MOSFET M12. The gate and the source of the MOSFET M12 are connected to the gate and the source of the MOSFET M14, respectively. The coupled sources of the MOSFETs M12 and M14 are connected to the ground. Thus, the MOSFETs M11 and M12 located at the input side are connected in cascode.
The drain and the source of the MOSFET M13 are connected to the terminal T2 and the drain of the MOSFET M14, respectively. The output terminal T3 of the active bias circuit 10 is connected to the point P2 at which the gate and the drain of the MOSFET M14 are coupled together. Thus, the MOSFETs M13 and M14 located at the output side also are connected in cascode.
A reference voltage V1 is applied to the terminal T1, thereby generating a reference current IREF flowing through the reference resistor R11. In other words, the reference current IREF is generated by the reference voltage V1 and the reference resistor R11. Since it can be considered that no gate current flows to the gates of the MOSFETs M11 and M13, the reference current IREF is equal to the drain current ID11 of the MOSFET M11 and to the drain current ID12 of the MOSFET M12 (i.e., IREF=ID11=ID12).
A bias voltage V2 is applied to the terminal T2, thereby generating the drain current ID13 of the MOSFET M13. The value of the drain current ID13 has a specific ratio with respect to that of the reference current IREF. Specifically, the value of the drain current ID13 is a times as much as that of the reference current IREF, where a is a positive constant (i.e., ID13=aIREF). Since it can be considered that no gate current flows to the gates of the MESFETs M12 and M14, the drain current ID13 is equal to the drain current ID14 of the MOSFET M14 (i.e., ID13=ID14).
The output bias voltage VOUT of the conventional bias circuit 10 is generated at the output terminal T3. The output bias voltage VOUT is equal to the voltage at the connection point P2 of the gate and the drain of the MOSFET M14 (i.e., the connection point of the drain of the MOSFET M14 and the source of the MOSFET M13).
A target circuit 20, to which the output bias voltage VOUT is applied from the active bias circuit 10, includes an n-channel enhancement MOSFET M15. The gate of the MOSFET M15 is connected to the output terminal T3 of the circuit 10, receiving the bias voltage VOUT of the circuit 10. The drain of the MOSFET M15 is connected to the terminal T4 to which a voltage VD is applied. The source of the MOSFET M15 is connected to the ground. Accordingly, the gate-to-source voltage of the MOSFET M15 is equal to the output bias voltage VOUT, which means that the drain current ID15 of the MOSFET M15 of the target circuit 20 increases or decreases according to the output bias voltage Vout of the bias circuit 10.
Although the target circuit 20 includes other active elements and passive elements along with the MOSFET M15, they are omitted in FIG. 1 for the sake of simplification.
The conventional active bias circuit 10 of FIG. 1 operates in the following way.
If the value of the reference resistor R11 is suitably determined or adjusted according to the value of the reference voltage V1 (e.g., 2V) applied to the terminal T1, the value of the reference current IREF flowing through the MOSFET M11 can be set as desired. Also, due to the reference current IREF thus set, the value of the voltage VP1 at the connection point P1 (i.e., the connection point of the resistor R11 and the drain of the MOSFET M11) is determined. In this case, the value of the voltage Vp2 at the connection point P2 (i.e., the output terminal T3) is given as the difference of the value of the forward voltage drop VFM13 of the MOSFET M13 from that of the bias voltage V2 applied to the terminal T2. Thus, the following equation (1) is established.
VP2=KOUT=V2xe2x88x92VFM13xe2x80x83xe2x80x83(1)
When the value of the reference voltage VREF applied to the terminal T1 (i.e., the reference current IREF) is changed, the values of the drain current ID13 of the MOSFET M13 and the forward voltage drop VFM13 thereof are changed, resulting in change of the output bias voltage VOUT. This means that even if the bias voltage V2 is not changed, the output bias voltage VOUT can be changed by changing the reference voltage V1.
In the target circuit 20, the value of the drain current ID15 of the MOSFET M15 varies according to the value of the output bias voltage VOUT applied to the gate of the MOSFET M15. Since the MOSFET M15 is of the enhancement type, the value of the drain current ID15 of the MOSFET M15 can be set as zero (i.e., 0 V) if the value of the output bias voltage VOUT is set to be lower than the threshold voltage of the MOSFET M15. Thus, the MOSFET M15 can be cut off.
The operation of the conventional bias circuit 10 shown in FIG. 1 scarcely fluctuates even if the threshold voltages Vth of the MOSFETs M11, M12, M13, and M14 fluctuate due to change of the various parameters in their fabrication process sequence and/or change of the ambient temperature of the circuit 10 during operation. In other words, as long as the parameters of the circuit 10 are kept unchanged, the value of the drain current IDD15 of the MOSFET M15 in the target circuit 20 is kept approximately constant in spite of the fluctuation of the threshold voltage and the ambient temperature.
For example, when the absolute values (i.e., amplitude) of the threshold voltages Vth of the MOSFETs M11, M12, M13, and M14 decrease, the value of the reference Current IREF increases according to the decrease of the threshold voltages Vth, lowering the voltage VP1 at the point P1 On the other hand, according to the increase of the reference current IREF, the drain current ID13 of the MOSFET M13 increases, which increases the voltage drop generated by the MOSFET M13. As a result, the value of the voltage VP2 at the point P2 (i.e., the output bias voltage VOUT of the circuit 10) decreases.
On the contrary, when the absolute values (i.e., amplitude) of the threshold voltages Vth of the MOSFETs M11, M12, M13, and M14 increase, the value of the reference current IREF decreases according to the increase of the threshold voltages Vth, raising the voltage VP1 at the point P1. On the other hand, according to the decrease of the reference current IREF, the drain current ID13 of the MOSFET M13 decreases, which decreases the voltage drop generated by the MOSFET M13. As a result, the value of the voltage VP2 at the point P2 (i.e., the output bias voltage VOUT) increases.
With the conventional bias circuit 10, in the above-described manner, the drain currents ID13 and ID14 Of the MOSFETs M13 and M14 (and therefore, the drain current ID15 of the MOSFET M15) are kept approximately constant against the fluctuation of the threshold voltages Vth,
The bias circuit 10 operates in the same way as above when the ambient temperature varies as well. Therefore, the drain current ID15 of the MOSFET M15 is kept approximately constant against the fluctuation of the ambient temperature.
However, the above-described conventional active bias circuit 10 shown in FIG. 1 has the following problems.
Specifically, with the conventional circuit 10, the power consumption of the target circuit 20 (i.e., the MOSFET M15) can be adjusted by changing the value of the reference voltage V1 applied to the terminal T1. This is due to the fact that the output bias voltage VOUT varies according to the change of the reference voltage V1, which changes the drain current ID15 of the MOSFET M15.
The bias circuit 10 is used, for example, for applying a desired bias voltage to a Radio-Frequency (RF) amplifier circuit provided in a mobile telephone or a cellular phone. In this case, the target circuit 20 is the RF amplifier circuit.
With mobile or cellular phones, generally, the voltage VD is supplied to the MOSFET M15 by way of the terminal T4 in the target circuit 20 and at the same time, the output bias voltage VOUT with a desired value is supplied by the bias circuit 10 to the MOSFET M15 of the target circuit 20 (i.e,, the RF amplifier circuit) in the normal operation. On the other hand, in the power-saving operation, the supply of the voltage VD to the MOSFET M15 is stopped with a switch (e.g., a so-called drain switch, not shown in FIG. 1) to stop temporarily the operation of the MOSFET M15 (and the circuit 20 itself).
Thus, there is a problem that the count (i.e., total number) of the necessary parts increases because the drain switch is essentially provided. Also, there is another problem that the switch necessitates specific electric power.
If the drain switch can be eliminated, these two problems are easily solved. This is realized by, for example, setting the output bias voltage VOUT of the bias circuit 10 to be lower than the threshold voltage of the MOSFET M15, thereby stopping the operation of the MOSFET 15 (i.e., the operation of the target circuit 20). However, some mobile telephones have a configuration that does not permit the reference voltage V1 of 0 V. In this case, it is unable to set the output bias voltage VOUT of the bias circuit 10 to be lower than the threshold voltage of the MOSFET M15, making the MOSFET M15 cut off. This means that there arises a problem that the lifetime or duration of the battery tends to be shortened.
Moreover, since the output bias voltage VOUT of the bias circuit 10 is unable to be sufficiently low, it is impossible or difficult for the MOSFET M15 to generate a sufficiently low RF output as desired. In other words, there is a problem that the variable range of the RF output of the MOSFET M15 by the reference voltage V1 is narrow.
Accordingly, an object of the present invention is to provide an active bias circuit that makes it possible to set the output bias voltage at approximately zero (0V) even if a reference voltage applied to generate a reference current does not reach the value of zero.
Another object of the present invention is to provide an active bias circuit that expands the variable range of the RF output of a target circuit that varies by changing the value of a reference voltage.
Still another object of the present invention is to provide an active bias circuit that makes it possible to cut off a current flowing in a target circuit including an enhancement active element or device without providing any cut-off switch.
The above objects together with others not specifically mentioned will become clear to those skilled in the art from the following description.
According to a first aspect of the present invention, an active bias circuit is provided, which comprises:
(a) a first transistor with a diode connection;
the first transistor being supplied with a reference current by way of a first resistor;
the first transistor having a control terminal;
(b) a second transistor connected in cascode to the first transistor;
the second transistor having a control terminal;
(c) a third transistor having a control terminal connected to the control terminal of the first transistor;
a constant current with a specific ratio with respect to the reference current flowing through the third transistor;
(d) a fourth transistor with a diode connection;
the fourth transistor being connected in cascode to the third transistor;
the fourth transistor having a control terminal connected to the control terminal of the second transistor;
(e) an output terminal formed between the third and fourth transistors connected in cascode;
an output bias voltage being derived from the output terminal;
the output bias voltage varying according to a reference voltage applied across the first and second transistors connected in cascode; and
(f) a second resistor connected between the control terminal of the first transistor and the control terminal of the third transistor;
wherein an absolute value of the output bias voltage is decreased with a voltage drop of the second resistor that is generated by a current flowing through the second resistor.
With the active bias circuit according to the first aspect of the present invention, the second resistor is provided between the control terminal of the first transistor and the control terminal of the third transistor. When a current flows through the second resistor, a specific voltage drop occurs. Therefore, by utilizing the voltage drop thus caused by the second resistor, the absolute value of the output bias voltage is decreased.
For example, when each of the first and third transistors is a FET, its control terminal is a gate. In this case, a leakage current flows through the second resistor between the gates of the two FETs (i.e., the first and third transistors) and therefore, a voltage drop is caused by the second resistor according to the value of the leakage current. On the other hand, when each of the first and third transistors is a bipolar transistor, its control terminal is a base. In this case, a base current flows through the second resistor between the bases of the two bipolar transistors and therefore, a voltage drop is caused by the second resistor according to the value of the base current. Consequently, the absolute value of the output bias voltage is decreased according to the value of the voltage drop thus caused.
As a result, even if the reference voltage applied to generate the reference current does not reach the value of zero (i.e., 0 V), the absolute value (i.e., amplitude) of the output bias voltage can be set at approximately zero. Thus, the current flowing through a target circuit, which is supplied with the output bias voltage from the active bias circuit of the first aspect, can be cut off without any dedicated switch for current cut-off.
Also, the absolute value of the output bias voltage is decreased according to that of the voltage drop of the second resistor. Therefore, the variable range of power consumption of the target circuit that varies by changing the value of the reference voltage can be expanded toward the low-value side. This means that the variable range of the REF output of the target circuit, which varies by changing the value of the reference voltage, is expanded.
In addition, the second resistor is connected between the control terminals of the first and third transistors. Therefore, the operation of the active bias circuit (i.e., the stable supply operation of the bias voltage) is not affected by insertion of the second resistor.
In a preferred embodiment of the circuit according to the first aspect, the absolute value of the output bias voltage reaches 0 V before the absolute value of the reference voltage reaches 0 V from a specific value.
In another preferred embodiment of the circuit according to the first aspect, the active bias circuit is so designed that the output bias voltage is applied to a control terminal of a voltage-driven active element operable in an enhanced mode provided in a target circuit. The absolute valve of the output bias voltage reaches a value for cutting off the element in the target circuit before the absolute value of the reference voltage reaches 0 V from a specific value.
According to a second aspect of the present invention, another active bias circuit is provided, which comprises:
(a) a first transistor with a diode connection;
the first transistor being supplied with a reference current by way of a first resistor;
the first transistor having a control terminal;
(b) a second transistor connected in cascode to the first transistor;
the second transistor having a control terminal;
(c) a third transistor having a control terminal connected to the control terminal of the first transistor;
a constant current with a specific ratio with respect to the reference current flowing through the third transistor;
(d) a fourth transistor with a diode connection;
the fourth transistor being connected in cascode to the third transistor;
the fourth transistor having a control terminal connected to the control terminal of the second transistor;
(e) an output terminal formed between the third and fourth transistors connected in cascode;
an output bias voltage being derived from the output terminal;
the output bias voltage varying according to a reference voltage applied across the first and second transistors connected in cascode; and
(f) a second resistor having a terminal connected to the control terminals of the second transistor and the fourth transistor in such a way that part of the current flowing through the third transistor flows through the second resistor to decrease a current flowing through the fourth transistor, thereby decreasing a voltage drop of the fourth transistor;
wherein an absolute value of the output bias voltage is decreased according to decrease of the voltage drop of the fourth transistor.
With the active bias circuit according to the second aspect of the present invention, the terminal of the second resistor is connected to the control terminals of the second transistor and the fourth transistor in such a way that part of the current flowing through the third transistor is shunted to the second resistor to decrease a current flowing through the fourth transistor, thereby decreasing the voltage drop of the fourth transistor. The absolute value of the output bias voltage is decreased according to decrease of the voltage drop of the fourth transistor.
As a result, even if the reference voltage applied to generate the reference current does not reach the value of zero (i.e., 0 V), the absolute value (i.e., amplitude) of the output bias voltage can be set at approximately zero. Thus, the current flowing through a target circuit, which is supplied with the output bias voltage from the active bias circuit of the second aspect, can be cut off without any dedicated switch for current cut-off.
Also, the absolute value of the output bias voltage is decreased according to the decrease of the voltage drop of the fourth transistor. Therefore, the variable range of power consumption of the target circuit that varies by changing the value of the reference voltage can be expanded toward the low-value side. This means that the variable range of the RF output of the target circuit, which varies by changing the value of the reference voltage, is expanded.
In addition, the second resistor has the terminal connected in common to the control terminals of the second and fourth transistors and then, the part of the current flowing through the third transistor is shunted to the second resistor. Therefore, the operation of the active bias circuit (i.e., the stable supply operation of the bias voltage) is not affected by insertion of the second resistor.
In a preferred embodiment of the circuit according to the second aspect, the second resistor has a resistance less than that of the fourth transistor. In this embodiment, a larger part of the current flowing through the third transistor is shunted to the second resistor, resulting in a large decrease of the voltage drop of the fourth transistor.
In another preferred embodiment of the circuit according to the second aspect, the absolute value of the output bias voltage reaches 0 V before the absolute value of the reference voltage reaches 0 V from a specific value.
In still another preferred embodiment of the circuit according to the second aspect, the active bias circuit is so designed that the output bias voltage is applied to a control terminal of a voltage-driven active element operable in an enhanced mode provided in a target circuit. The absolute value of the output bias voltage reaches a value for cutting off the element in the target circuit before the absolute value of the reference voltage reaches 0 V from a specific value.